Texas Instruments MSP430x1xx - Manual (Page 92)

Hardware Multiplier Operation
6-4
The sum extension register contents differ, depending on the operation and
on the results of the operation.
Table 6–1. Sum Extension Register Contents
Register MPY MPYS MAC MACS, see Notes
Operand1 x + – + + (OP1
×
OP2 +
ACC)
≤
(OP1
×
OP2 +
ACC) >
(OP1
×
OP2 +
ACC) >
(OP1
×
OP2 +
ACC)
≤
Operand2 x + – – –
ACC)
≤
0FFFFFFFFh
ACC) >
0FFFFFFFFh ACC) >
07FFFFFFFh ACC)
≤
07FFFFFFFh
SumExt 0000h 0000h 0FFFFh 0000h 0001h 0FFFFh 0000h
Note: The following two overflow conditions may occur when using the MACS function and should be handled by software or
avoided.
1) The result of a MACS operation is positive and larger than 07FFF FFFFh. In this case, the SumExt register contains
0FFFFh and the ACC register contains a negative number (8000 0000h .... 0FFFF FFFFh).
2) The result of a MACS operation is negative and less than or equal to 07FFF FFFFh. In this case, the SumExt register
contains 0000h and the ACC register contains a positive number (0000 0000h ... 07FFF FFFFh).