Texas Instruments MSP430x1xx - Manual (Page 39)

Interrupt Processing
3-9
System Resets, Interrupts, and Operating Modes
3.3.2 Operation of Global Interrupt—Oscillator Fault Control
The oscillator fault signal warns of a possible error condition with the crystal
oscillator.
3.3.2.1 Oscillator Fault Control in the Basic Clock System
The oscillator-fault signal is triggered when the LFXT1 oscillator is configured
to run in HF mode but is not running, stops running after being operational, or
is switched off. The oscillator-fault signal is also triggered under the same
conditions for the XT2 oscillator, present in some devices. Note that a PUC sig-
nal can trigger an oscillator fault, because the PUC switches the LFXT1 to LF
mode, therefore switching off the HF mode. The PUC signal also switches off
the XT2 oscillator.
The oscillator fault signal can be enabled to generate an NMI by bit OFIE in
the SFRs. The interrupt flag OFIFG in the SFRs can then be tested by the
interrupt service routine to determine if the NMI was caused by an oscillator
fault. See Basic Clock Module chapter for more details on the operation of the
crystal oscillators LFXT1 and XT2.
3.4 Interrupt Processing
The MSP430 programmable interrupt structure allows flexible on-chip and
external interrupt configurations to meet real-time interrupt-driven system
requirements. Interrupts may be initiated by the processor’s operating
conditions such as watchdog overflow; or by peripheral modules or external
events. Each interrupt source can be disabled individually by an interrupt
enable bit, or all maskable interrupts can be disabled by the general interrupt
enable (GIE) bit in the status register.
Whenever an interrupt is requested and the appropriate interrupt enable bit
and general interrupt enable (GIE) bit are set, the interrupt service routine
becomes active as follows:
1) CPU active: The currently executing instruction is completed.
2) CPU stopped: The low-power modes are terminated.
3) The program counter pointing to the next instruction is pushed onto the
stack.
4) The status register is pushed onto the stack.
5) The interrupt with the highest priority is selected if multiple interrupts
occurred during the last instruction and are pending for service.
6) The appropriate interrupt request flag resets automatically on single-
source flags. Multiple source flags remain set for servicing by software.
7) The GIE bit is reset; the CPUOff bit, the OscOff bit, and the SCG1 bit are
cleared; the status bits V, N, Z, and C are reset. SCG0 is left unchanged.