Texas Instruments MSP430x1xx - Manual (Page 168)

Timer_A Registers
10-28
Bit 3: Capture/compare input signal CCIx:
The selected input signal (CCIxA, CCIxB, V
CC
. or GND) can be
read by this bit. See Figure 10–18.
Bit 4: Interrupt enable CCIEx: Enables or disables the interrupt
request signal of capture/compare block x. Note that the GIE bit
must also be set to enable the interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bits 5 to 7: Output mode select bits:
Table 10–7 describes the output mode selections.
Table 10–7.Capture/Compare Control Register Output Mode
Bit
Value
Output Mode Description
0 Output only The OUTx signal reflects the value of the OUTx bit
1 Set EQUx sets OUTx
2 PWM toggle/reset EQUx toggles OUTx. EQU0 resets OUTx.
3 PWM set/reset EQUx sets OUTx. EQU0 resets OUTx
4 Toggle EQUx toggles OUTx signal.
5 Reset EQUx resets OUTx.
6 PWM toggle/set EQUx toggles OUTx. EQU0 sets OUTx.
7 PWM reset/set EQUx resets OUTx. EQU0 sets OUTx.
Note: OUTx updates with rising edge of timer clock for all modes except mode 0.
Modes 2, 3, 6, 7 not useful for output unit 0.
Bit 8: CAP sets capture or compare mode.
0: Compare mode
1: Capture mode
Bit 9: Read only, always read as 0.
Bit 10: SCCIx bit:
The selected input signal (CCIxA, CCIxB, V
CC
, or GND) is
latched with the EQUx signal into a transparent latch and can be
read via this bit.
Bit 11: SCSx bit:
This bit is used to synchronize the capture input signal with the
timer clock.
0: asynchronous capture
1: synchronous capture
Bits 12, 13: Input select, CCIS0 and CCIS1:
These two bits define the capture signal source. These bits are
not used in compare mode.
0
Input CCIxA is selected
1 Input CCIxB is selected
2 GND
3 V
CC