Texas Instruments MSP430x1xx - Manual (Page 254)

Synchronous Operation
13-8
13.3.1.1 Four-Pin SPI Master Mode
The signal on STE is used by the active master to prevent bus conflicts with
another master. The STE pin is an input when the corresponding PnSEL bit
(in the I/O registers) selects the module function. The master operates
normally while the STE signal is high. Whenever the STE signal is low, for
example, when another device makes a request to become master, the actual
master reacts such that:
- The pins that drive the SPI bus lines SIMO and UCLK are set to inputs.
- The error bit FE and the interrupt flag URXIFG in register URCTL are set.
The bus conflict is then removed: SIMO and UCLK do not drive the bus lines,
and the error flag indicates the system integrity violation to the software. Pins
SIMO and UCLK are forced to the input state while STE is in a low state, and
they return to the conditions defined by the corresponding control bits when
STE returns to a high state.
In the three-pin mode, the STE input signal is not relevant.
13.3.2 Slave SPI Mode
The slave mode is selected when bit MM of the control register is reset and
synchronous mode is selected.
The UCLK pin is used as the input for the serial-shift clock supplied by an
external master. The data-transfer rate is determined by this clock and not by
the internal bit-rate generator. The data, loaded into the transmit shift register
through the transmit buffer (UTXBUF) before the start of UCLK, is transmitted
on the SOMI pin using the UCLK supplied from the master. Simultaneously,
the serial data applied to the SIMO pin are shifted into the receive shift register
on the opposite edge of the clock.
The receive-interrupt flag URXIFG indicates when the data is received and
transferred into the receive buffer. The overrun-error bit is set when the
previously-received data is not read before the new data is written to the
receive buffer.
13.3.2.1 Four-Pin SPI Slave Mode
In the four-pin SPI mode, the STE signal is used by the slave to enable the
transmit and receive operations. It is applied from the SPI master. The receive
and transmit operations are disabled when the STE signal is high, and enabled
when it is low. Whenever the STE signal becomes high, any receive operation
in progress is halted and then continues when the STE signal is low again. The
STE signal enables one slave to access the data lines. The SOMI is input if
STE is set high.