Texas Instruments MSP430x1xx - Manual (Page 170)

Timer_A Registers
10-30
10.6.4.2 Vector Word, TAIFG, CCIFG1 to CCIFG4 Flags
The CCIFGx (other than CCIFG0) and TAIFG interrupt flags are prioritized and
combined to source a single interrupt as shown in Figure 10–31. The interrupt
vector register TAIV (shown in Figure 10–32) is used to determine which flag
requested an interrupt.
Figure 10–31. Schematic of Capture/Compare Interrupt Vector Word
S
S
Sel
R
CCI1
EQ1
CMP1
Timer Clock
IRACC
CCIE1
CCIFG1
S
S
Sel
R
CCI2
EQ2
CMP2
Timer Clock
IRACC
CCIE2
CCIFG2
S
S
Sel
R
CCI3
EQ3
CMP3
Timer Clock
IRACC
CCIE3
CCIFG3
S
S
Sel
R
CCI4
EQ4
CMP4
Timer Clock
IRACC
CCIE4
CCIFG4
S
S
Sel
R
Timer FFFF
Timer = CCR0
XXX
Timer Clock
IRACC
TAIE
TAIFG
Priority and
Vector Word
Generator
Interrupt_Service_Request
Interrupt_Vector_Address
14x Devices Only
Figure 10–32. Vector Word Register
r0
15 0
TAIV
12Eh
0
r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0
0 0 0 0 0 0 0 0 0 0 Interrupt Vector 0
r-(0) r-(0) r-(0)
0
The flag with the highest priority generates a number from 2 to 12 in the TAIV
register as shown in Table 10–9. (If the value of the TAIV register is 0, no
interrupt is pending.) This number can be added to the program counter to
automatically enter the appropriate software routine without the need for
reading and evaluating the interrupt vector. The software example in section
10.6.4.3 shows this technique.