Texas Instruments MSP430x1xx User Manual
Page 86
Instruction Set Overview
5-22
Table 5–18. Emulated Instructions (Continued)
Mnemonic
Description
Status Bits
Emulation
V
N
Z
C
Data Instructions (common use) (continued)
TST[.W]
dst
Test destination
0
*
*
*
CMP
#0,dst
TST.B
dst
Test destination
0
*
*
*
CMP.B
#0,dst
Program Flow Instructions
BR
dst
Branch to . . .
–
–
–
–
MOV
dst,PC
DINT
Disable interrupt
–
–
–
–
BIC
#8,SR
EINT
Enable interrupt
–
–
–
–
BIS
#8,SR
NOP
No operation
–
–
–
–
MOV
#0h,#0h
RET
Return from subroutine
–
–
–
–
MOV
@SP+,PC
5.3.5
Miscellaneous
Instructions without operands, such as CPUOff, are not provided. Their
functions are switched on or off by setting or clearing the function bits in the
status register or the appropriate I/O register. Other functions are emulated
using dual operand instructions.
Some examples are as follows:
BIS
#28h,SR
; Enter OscOff mode
; + Enable general interrupt (GIE)
BIS
#18h,SR
; Enter CPUOff mode
; + Enable general interrupt (GIE)