Texas Instruments MSP430x1xx - Manual (Page 193)

Timer Modes
11-17
Timer_B
Applications with slow timer clocks can use the nonsynchronized capture
signal. In this scenario the software can validate the data and correct it if
necessary as shown in the following example:
; Software example for the handling of asynchronous
; capture signals
;
; The data of the capture/compare register CCRx are taken
; by the software in the according interrupt routine
; – they are taken only after a CCIFG was set.
; The timer clock is much slower than the system clock
; MCLK.
;
CCRx_Int_hand ...
; Start of interrupt
; handler
...
...
CMP
&CCRx,&TBR ; Test if the data
; CCRX = TBR
JEQ Data_Valid
MOV
&TBR,&CCRx ; The data in CCRx is
; wrong, use the timer data
Data_Valid ... ... ; The data in CCRx are valid
...
...
RETI
;
Overflow logic is provided with each capture/compare register to flag the user
if a second capture is performed before data from the first capture was read
successfully. Bit COVx in register CCTLx is set when this occurs as shown in
Figure 11–20.
Figure 11–20.Capture Cycle
Second
Capture
Taken
COV = 1
Capture
Taken
No
Capture
Taken
Read
Taken
Capture
Clear Bit COV
in Register CCTL
Idle
Idle
Capture
Capture Read and No Capture
Capture
Capture Read Capture