Texas Instruments MSP430x1xx - Manual (Page 175)

Timer_A UART
10-35
Timer_A
One capture/compare block is used when half-duplex communication mode
is desired. Two capture/compare blocks are used for full-duplex mode.
Figure 10–34 illustrates the capture/compare timing for the UART.
Figure 10–34. Timer_A UART Timing
URXD Signal
Capture
Compare
Receive
UTXD Signal
Transmit
Capture
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A complete application note including connection diagrams and complete soft-
ware listing may be found at
www.ti.com/sc/msp430.