Texas Instruments MSP430x1xx - Manual (Page 351)

B-1
Instruction Set Description
Instruction Set Description
The MSP430 core CPU architecture evolved from a reduced instruction set
with highly-transparent instruction formats. Using these formats, core
instructions are implemented into the hardware. Emulated instructions are
also supported by the assembler. Emulated instructions use the core
instructions with the built-in constant generators CG1 and CG2 and/or the
program counter (PC). The core and emulated instructions are described in
detail in this section. The emulated instruction mnemonics are listed with
examples.
Program memory words used by an instruction vary from one to three words,
depending on the combination of addressing modes.
Topic Page
B.1 Instruction Set Overview B-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B.2 Instruction Set Description B-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix B