Texas Instruments MSP430x1xx - Manual (Page 310)

Conversion Modes
15-20
The intermediate modes are caused by the asynchronous clocks for the CPU
and the ADC12. These intermediate modes can be avoided simply by chang-
ing only one CONSEQ bit per instruction. For example, to change from mode
0 to mode 3 while the converter is actively running, the following instructions
could be used:
BIS #CONSEQ_0,&ADC12CTL1 ; Example: 0
→
3, first
; step is 0
→
1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIS #CONSEQ_1,&ADC12CTL1 ; second step is 1
→
3 . . .
Acceptable sequence modifications are: 0
→
1, 0
→
2, 1
→
0, 1
→
3, 2
→
0,
2
→
3, 3
→
1, and 3
→
2.
15.5.6 Power Down
The ADC12 incorporates two bits (ADC12ON and REFON) for power savings.
ADC12ON turns on the A/D core and REFON turns on the reference genera-
tor. Each bit is individually controllable by software. The ADC12 is turned off
completely if both bits are reset. The ADC12 registers are not affected by either
of these bits and can be accessed and modified at any time (see the
ADC12
Control Registers section). Note, however, that ADC12ON and REFON may
only be modified if ENC=0.
Additionally, other ADC12 functions are automatically switched on and off as
needed—if possible—to realize additional power savings – even while the
ADC12 is running.
Caution! Do not power-down the converter or the reference
generator while the converter is active. Conversion results will be
false.
It is possible to disable the reference generator and the ADC12 by
resetting bits ADC12ON and REFON before an active conversion or
sequence of conversions has completed. For example, if the
conversion mode is set to sequence-of-channels, and software
resets the ENC bit immediately after the sequence begins, the
ADC12ON and REFON bits can then be reset before the sequence
completes. If this occurs, the ADC12 will be powered down
immediately and the conversion results will be false.