Texas Instruments MSP430x1xx User Manual
Page 243
Baud Rate Considerations
12-27
USART Peripheral Interface, UART Mode
Example 12–3. Error Example for 2400 Baud
The following data are assumed:
Baud rate =
2400
BRCLK =
32,768 Hz (ACLK)
UBR =
13, since the ideal division factor is 13.67
m = 6Bh:
m7 = 0, m6 = 1, m5 = 1, m4 = 0, m3 = 1, m2 = 0, m1 = 1
and m0 = 1
The LSB (m0) of the modulation register is used first.
Start bit Error [%]
+
ǒ
baud rate
BRCLK
((0
)
1)
UBR
)
1)–1
Ǔ
100%
+
2.54%
Data bit D0 Error [%]
+
ǒ
baud rate
BRCLK
((1
)
1)
UBR
)
2)–2
Ǔ
100%
+
5.08%
Data bit D1 Error [%]
+
ǒ
baud rate
BRCLK
((2
)
1)
UBR
)
2)–3
Ǔ
100%
+
0.29%
Data bit D2 Error [%]
+
ǒ
baud rate
BRCLK
((3
)
1)
UBR
)
3)–4
Ǔ
100%
+
2.83%
Data bit D3 Error [%]
+
ǒ
baud rate
BRCLK
((4
)
1)
UBR
)
3)–5
Ǔ
100%
+*
1.95%
Data bit D4 Error [%]
+
ǒ
baud rate
BRCLK
((5
)
1)
UBR
)
4)–6
Ǔ
100%
+
0.59%
Data bit D5 Error [%]
+
ǒ
baud rate
BRCLK
((6
)
1)
UBR
)
5)–7
Ǔ
100%
+
3.13%
Data bit D6 Error [%]
+
ǒ
baud rate
BRCLK
((7
)
1)
UBR
)
5)–8
Ǔ
100%
+ *
1.66%
Data bit D7 Error [%]
+
ǒ
baud rate
BRCLK
((8
)
1)
UBR
)
6)–9
Ǔ
100%
+
0.88%
Parity bit Error [%]
+
ǒ
baud rate
BRCLK
((9
)
1)
UBR
)
7)–10
Ǔ
100%
+
3.42%
Stop bit 1 Error [%]
+
ǒ
baud rate
BRCLK
((10
)
1)
UBR
)
7)–11
Ǔ
100%
+ *
1.37%
Stop bit 2 Error [%]
+
ǒ
baud rate
BRCLK
((11
)
1)
UBR
)
8)–12
Ǔ
100%
+
1.17%
12.7.2 Typical Baud Rates and Errors
The standard baud rate data needed for the baud rate registers and the
modulation register are listed in Table 12–6 for the 32,768-Hz watch crystal
(ACLK) and SMCLK, assumed to be 32 times the ACLK frequency. The error
listed is calculated for the transmit and receive paths. In addition to the error
for the receive operation, the synchronization error must be considered.