Texas Instruments MSP430x1xx - Manual (Page 229)

Interrupt and Enable Functions
12-13
USART Peripheral Interface, UART Mode
12.4.3 USART Receive Interrupt Operation
In the receive interrupt operation, shown in Figure 12–14, the receive interrupt
flag URXIFG is set or is unchanged each time a character is received and
loaded into the receive buffer:
- Erroneous characters (parity, frame, or break error) do not set interrupt
flag URXIFG when URXEIE is reset: URXIFG is unchanged.
- All types of characters (URXWIE = 0), or only address characters
(URXWIE = 1), set the interrupt flag URXIFG. When URXEIE is set,
erroneous characters can also set the interrupt flag URXIFG.
Figure 12–14. Receive Interrupt Operation
Clear
URXS
Clear
τ
(S)
SYNC
Valid Start Bit
Receiver Collects Character
URXSE
From URXD
SYNC
PE
FE
BRK
URXEIE
URXWIE
RXWake
Erroneous Character
Will Not Set Flag URXIFG
Each Character or Address
Will Set Flag URXIFG
Character Received
or
Break Detected
URXIFG
URXIE
Request_
Interrupt_Service
SWRST
PUC
URXBUF
URXSE
IRQA
URXIFG is reset by a system reset PUC signal, or with a software reset
(SWRST). URXIFG is reset automatically if the interrupt is served
(URXSE = 0) or the receive buffer URXBUF is read. A set receive interrupt flag
URXIFG indicates that an interrupt event is waiting to be served. A set receive
interrupt enable bit URXIE enables serving a waiting interrupt request. Both
the receive interrupt flag URXIFG and the receive interrupt enable bit URXIE
are reset with the PUC signal and a SWRST.
Signal URXIFG can be accessed by the software, whereas signal URXS
cannot. When both interrupt events—character receive action and receive
start detection—are enabled by the software, the flag URXIFG indicates that
a character was received but the start-detect interrupt was not. Because the
interrupt software handler for the receive start detection resets the URXSE bit,
this clears the URXS bit and prevents further interrupt requests from URXS.
The URXIFG should already be reset since no set condition was active during
URXIFG latch time.