Texas Instruments MSP430x1xx - Manual (Page 257)

Interrupt and Control Functions
13-11
USART Peripheral Interface, SPI Mode
Figure 13–9. State Diagram of Receive Enable—MSP430 as Slave, Four-Pin Mode
Idle State
(Receive
Enabled)
Receive
Disable
Receiver
Collects
Character
USPIE = 0
No Clock at UCLK
Not Completed
USPIE = 1
and STE = 0
USPIE = 0
USPIE = 1
Handle Interrupt
Conditions
Character
Received
USPIE = 1
USPIE = 0
SWRST
PUC
External Clock
Present
USPIE = 1
13.4.2 USART Receive/Transmit Enable Bit, Transmit Operation
The receive/transmit enable bit USPIE, shown in Figures 13–10 and 13–11,
enables or disables the shifting of a character on the serial data line. If this bit
is reset, the transmitter is disabled, but any active transmission does not halt
until all data previously written to the transmit buffer is transmitted. If the
transmission is completed, any further write operation to the transmitter buffer
does not transmit. When the UTXBUF is ready, any pending request for
transmission remains, which results in an immediate start of transmission
when USPIE is set and the transmitter is empty. A low state on the STE signal
removes the active master (four-pin mode) from the bus. It also indicates that
another master is requesting the active-master function.
13.4.2.1 Receive/Transmit Enable—MSP430 as Master
Figure 13–10 shows the transmit-enable activity when the MSP430 is master.
Figure 13–10. State Diagram of Transmit Enable—MSP430 as Master
Idle State
(Transmitter
Enabled)
Transmit
Disable
Transmission
Active
USPIE = 0
No Data Written
to Transfer Buffer
Not Completed
USPIE = 1
USPIE = 1
USPIE = 0
USPIE = 1,
Data Written to
Transmit Buffer Handle Interrupt
Conditions
Character
Transmitted
USPIE = 1
USPIE = 0 And Last Buffer
Entry Is Transmitted
SWRST
PUC