Texas Instruments MSP430x1xx - Manual (Page 271)

Comparator_A Description
14-5
Comparator_A
14.2.6 Comparator_A Interrupt Circuitry
One interrupt and one interrupt vector are associated with the Comparator_A
(see Figure 14–3). The interrupt flag CAIFG is set on either the rising or falling
edge of the comparator output. The interrupt edge-select bit, CAIES, deter-
mines which edge of the output signal sets the CAIFG flag. The interrupt-en-
able bit, CAIE, along with the general interrupt-enable bit (GIE) control if the
CAIFG bit generates a CPU interrupt. If both the CAIE and the GIE bits are set,
then the CAIFG flag will generate a CPU interrupt request. The CAIFG flag is
automatically reset when the CPU interrupt request is serviced. The CAIFG,
CAIES, and CAIE bits are all located in the CACTL1 register.
Figure 14–3. Comparator_A Interrupt System
0
1
CAF
CCI1B
CAOUT
Set
CAIFG
0
1
CAIES
Reset
VCC
CAIE
D Q
Set
IRQ, Interrupt Service Request
IRACC, Interrupt Request Accepted
τ ∼
2
µ
s
POR