Texas Instruments MSP430x1xx - Manual (Page 189)

Timer Modes
11-13
Timer_B
The count direction is always latched with a flip-flop (Figure 11–14). This is
useful because it allows the user to stop the timer and then restart it in the same
direction it was counting before it was stopped. For example, if the timer was
counting down when the MCx bits were reset, then it will continue counting in
the down direction if it is restarted in up/down mode. If this is not desired, the
CLR bit in the TBCTL register must be used to clear the direction. Note that
the CLR bit affects other setup conditions of the timer. Refer to Section 11.6
for a discussion of the Timer_B registers.
Figure 11–14.Timer Up/Down Direction Control
Set
D Q
Reset
POR CLR
in TBCTL
Up/Down For
Timer TBR
Low: Down Direction
High: Up Direction
Up/Down Mode
TBR => TBCL0
Timer Clock
In up/down mode, the interrupt flags (CCIFG0 and TBIFG) are set at equal time
intervals (Figure 11–15). Each flag is set only once during the period, but they
are separated by 1/2 the timer period. CCIFG0 is set when the timer
counts
from TBCL0–1 to TBCL0, and TBIFG is set when the timer completes counting
down from 0001h to 0000h. Each flag is capable of producing a CPU interrupt
when enabled.
Figure 11–15.Up/Down Mode Flag Setting
TBCL0–1 TBCL0 2h 1h 0h 1h
Timer
Clock
Timer
Set
TBIFG
Set
CCIFG0
TBCL0–1 TBCL0–2
Up/Down
11.3.4.1 Timer In Up/Down Mode—Changing the Value of Period Register TBCL0,
Immediate Mode for TBCL0
Changing the period value while the timer is running in up/down mode and the
transfer mode for TBCL0 is
immediate is even trickier than in up mode. Like
in up mode, the phase of the timer clock when TBCL0 is changed affects the
timer’s behavior. Additionally, in up/down mode, the direction of the timer also
affects the behavior.
If the timer is counting in the up direction when the new period is transferred
from CCR0 to TBCL0, the conditions in the up/down mode are identical to