Texas Instruments MSP430x1xx - Manual (Page 128)

Ports P1, P2
8-8
8.2.3 Port P1, P2 Interrupt Control Functions
Ports P1 and P2 use eight bits for interrupt flags, eight bits to enable interrupts,
eight bits to select the effective edge of an interrupt event, one interrupt vector
address for port P1, and one interrupt vector address for port P2.
Each signal uses three bits for configuration and interrupt:
- Interrupt flag, P1IFG.0 to P1IFG.7 and P2IFG.0 to P2IFG.7
- Interrupt enable bit, P1IE.0 to P1IE.7 and P2IE.0 to P2IE.7
- Interrupt edge select bit, P1IES.0 to P1IES.7 and P2IES.0 to P2IES.7
The interrupt flags P1IFG.0 to P1IFG.7 source one interrupt and P2IFG.0 to
P2IFG.7 source one interrupt. Any interrupt event on one or more pins of P1.0
to P1.7 or P2.0 to P2.7 requests an interrupt when two conditions are met: the
appropriate individual bit PnIE.x is set, and the GIE bit is set. Interrupt flags
P1IFG.0 to P1IFG.7 or P2IFG.0 to P2IFG.7 are not automatically reset. The
software of the interrupt service routine should handle the detection of the
source, and reset the appropriate flag when it is serviced.