Texas Instruments MSP430x1xx - Manual (Page 138)

The Watchdog Timer
9-6
When the module is used in watchdog mode, the software should periodically
reset the WDTCNT by writing a 1 to bit CNTCL of WDTCTL to prevent
expiration of the selected time interval. If a software problem occurs and the
time interval expires because the counter is no longer being reset, a system
reset is generated and a system PUC signal is activated. The system restarts
at the same program address that follows a power up. The cause of reset can
be determined by testing bit 0 of interrupt flag register 1 in the SFRs. The
appropriate time interval is selected by setting bits SSEL, IS0, and IS1
accordingly.
9.1.3.2 Timer Mode
Setting WDTCTL register bit TMSEL to 1 selects the timer mode. This mode
provides periodic interrupts at the selected time interval. A time interval can
also be initiated by writing a 1 to bit CNTCL in the WDTCTL register.
When the WDT is configured to operate in timer mode, the WDTIFG flag is set
after the selected time interval, and it requests a standard interrupt service.
The WDT interrupt flag is a single-source interrupt flag and is automatically
reset when it is serviced. The enable bit remains unchanged. In interval-timer
mode, the WDT interrupt-enable bit and the GIE bit must be set to allow the
WDT to request an interrupt. The interrupt vector address in timer mode is
different from that in watchdog mode.
Note: Watchdog Timer, Changing the Time Interval
Changing the time interval without clearing the WDTCNT may result in an
unexpected and immediate system reset or interrupt. The time interval must
be changed together with a counter-clear command using a single
instruction (for example, MOV #05A0Ah,&WDTCTL).
Changing the clock source during normal operation may result in an incorrect
interval. The timer should be halted before changing the clock source.
9.1.3.3 Operation in Low-Power Modes
The MSP430 devices have several low-power modes. Different clock signals
are available in different low-power modes. The requirements of the user’s
application and the type of clocking circuit on the MSP430 device determine
how the Watchdog Timer and clocking signals should be configured. Review
the device data sheet and clock-system chapter to determine the clocking
circuit, clock signals, and low-power modes available. For example, the WDT
should not be configured in watchdog mode with SMCLK as its clock source
if the user wants to use low-power mode 3 because SMCLK is not active in
LPM3, therefore the WDT would not function properly.
The WDT hold condition can also be used to support low power operation. The
hold condition can be used in conjunction with low-power modes when
needed.