Texas Instruments MSP430x1xx - Manual (Page 263)

Control and Status Registers
13-17
USART Peripheral Interface, SPI Mode
Bit 0: Master mode:
The transmitter-empty flag TXEPT is set when the transmitter
shift register and UTXBUF are empty, and reset when data are
written to UTXBUF. It is set again by a SWRST.
Slave mode:
The transmitter-empty flag TXEPT is not set when the trans-
mitter shift register and UTXBUF are empty.
Bit 1: The slave transmit-control bit STC selects if the STE pin is used
for master and slave mode:
STC = 0:
The four-pin mode of SPI is selected. The STE
signal is used by the master to avoid bus conflicts,
or is used in slave mode to control transmit and
receive enable.
STC = 1: The three-pin SPI mode is selected. STE is not
used in master or slave mode.
Bit 2: Unused
Bit 3: Unused
Bits 4, 5: Source select 0 and 1
The source-select bits define which clock source is used for
baud-rate generation only when master mode is selected:
SSEL1,SSEL0
0 External clock UCLK selected
1 Auxiliary clock ACLK selected
2, 3 SMCLK selected
In master mode (MM = 1), an external clock at UCLK cannot be
selected since the master supplies the UCLK signal for any
slave. In slave mode, bits SSEL1 and SSEL0 are not relevant.
The external clock UCLK is always used.
Bits 6, 7: Clock polarity CKPL and clock phase CKPH
The CKPL bit controls the polarity of the SPICLK signal.
CKPL = 0:
The inactive level is low; data is output with the
rising edge of UCLK; input data is latched with
the falling edge of UCLK.
CKPL = 1: The inactive level is high; data is output with the
falling edge of UCLK; input data is latched with
the rising edge of SPICLK.
The CKPH bit controls the polarity of the SPICLK signal as
shown in Figure 13–17.
CKPH = 0:
Normal UCLK clocking scheme
CKPH = 1: UCLK is delayed by one half cycle