Texas Instruments MSP430x1xx - Manual (Page 209)

Timer_B Registers
11-33
Timer_B
Bit 0: Capture/compare interrupt flag CCIFGx
Capture mode:
If set, it indicates that a timer value was captured in the
CCRx register.
Compare mode:
If set, it indicates that a timer value was equal to the data
in the TBCLx latch.
CCIFG0 flag:
CCIFG0 is automatically reset when the interrupt request
is accepted.
CCIFG1 to CCIFGx flags:
The flag that caused the interrupt is automatically reset
after the TBIV word is accessed. If the TBIV register is not
accessed, the flags must be reset with software.
No interrupt is generated if the corresponding interrupt
enable bit is reset, but the flag will be set. In this scenario,
the flag must be reset by the software.
Setting the CCIFGx flag with software will request an
interrupt if the interrupt-enable bit is set.
Bit 1: Capture overflow flag COV
Compare mode selected, CAP = 0:
Capture signal generation is reset. No compare event will
set COV bit.
Capture mode selected, CAP = 1:
The overflow flag COV is set if a second capture is
performed before the first capture value is read. The
overflow flag must be reset with software. It is not reset by
reading the capture value.
Bit 2: The OUTx bit determines the value of the OUTx signal if the
output mode is 0.
Bit 3: Capture/compare input signal CCIx:
The selected input signal (CCIxA, CCIxB, V
CC
. or GND) can be
read by this bit. See Figure 11–18.
Bit 4: Interrupt enable CCIEx: Enables or disables the interrupt
request signal of capture/compare block x. Note that the GIE bit
must also be set to enable the interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bits 5 to 7: Output mode select bits:
Table 11–7 describes the output mode selections.