Texas Instruments MSP430x1xx User Manual
Page 322
ADC12 Control Registers
15-32
ADC12TOVIE
bit2
Conversion-time-overflow interrupt enable.
The timing overflow happens if another sample-and-conversion is
requested while the current conversion is not completed. This is
independent of the conversion modes selected by CONSEQ. If the timing
overflow vector is generated and the timing overflow interrupt enable flag
ADC12TOVIE and the general interrupt enable bit GIE are set, an interrupt
service is requested. There is no individual interrupt flag. See the
ADC12
Interrupt Vector Register ADC12IV section for more information on ADC12
interrupts.
ADC12OVIE
bit3
Overflow-interrupt enable. Individual enable for the overflow-interrupt
vector.
The overflow happens if a conversion result is written into an ADC memory
ADC12MEMx but the previous result was not read. An interrupt service is
requested if the overflow vector is generated, the overflow-interrupt-enable
flag ADC12OVIE is set, and the general-interrupt-enable bit GIE is set.
There is no individual interrupt flag. See the
ADC12 Interrupt Vector
Register ADC12IV section for more information on ADC12 interrupts.
ADC12ON
bit4
Turn on the 12-bit ADC core. Settling-time constraints must be met when the
ADC12 core is powered up.
0:
Power consumption of the core is off. No conversion will be started.
1:
ADC core is supplied with power. If no A/D conversion is needed,
ADC12ON can be reset to conserve power.
REFON
bit5
Reference voltage ON.
0:
The internal-reference voltage is switched off. No power is consumed
from the reference-voltage generator.
1:
The internal-reference voltage is switched on. The reference-voltage
generator consumes power. When the reference generator is switched
on, the settling time of the reference voltage must be completed before
the first sampling and conversion is started.
2_5V
bit6
Reference-voltage level.
0:
The internal reference voltage is 1.5V, if REFON = 1.
1:
The internal reference voltage is 2.5V, if REFON = 1.
MSC
bit7
Multiple sample and conversion. Valid only when the sample timer is
selected to generate the SAMPCON signal (SHP=1) and the A/D mode is
chosen as repeat-single-channel, sequence-of-channel or repeat-
sequence-of-channels (CONSEQ
≠
0).
0:
The sampling timer requires a rising edge of the SHI signal to trigger
each sample-and-conversion.
1:
The first rising edge of the SHI signal triggers the sampling timer, but
further sample-and-conversion are performed automatically as soon as
the prior conversion is completed—without additional rising edges of
SHI. Additional rising edges of SHI are ignored until the sequence has
completed or the ENC bit has been toggled (depending on mode).