Texas Instruments MSP430x1xx - Manual (Page 160)

Timer Modes
10-20
10.5.1 Output Unit—Output Modes
The output modes are defined by the OMx bits and are discussed below. The
OUTx signal is changed with the rising edge of the timer clock for all modes
except mode 0. Output modes 2, 3, 6, and 7 are not useful for output unit 0.
Output mode 0: Output mode:
The output signal OUTx is defined by the OUTx bit in control
register CCTLx. The OUTx signal updates immediately
upon completion of writing the bit information.
Output mode 1: Set mode:
The output is set when the timer value becomes equal to
capture/compare data CCRx. It remains set until a reset of
the timer, or until another output mode is selected that
controls the output.
Output mode 2: PWM toggle/reset mode:
The output is toggled when the timer value becomes equal
to capture/compare data CCRx. It is reset when the timer
value becomes equal to CCR0.
Output mode 3: PWM set/reset mode:
The output is set when the timer value becomes equal to
capture/compare data CCRx. It is reset when the timer value
becomes equal to CCR0.
Output mode 4: Toggle mode:
The output is toggled when the timer value becomes equal
to capture/compare data CCRx. The output period is double
the timer period.
Output mode 5: Reset mode:
The output is reset when the timer value becomes equal to
capture/compare data CCRx. It remains reset until another
output mode is selected that controls the output.
Output mode 6: PWM toggle/set mode:
The output is toggled when the timer value becomes equal
to capture/compare data CCRx. It is set when the timer
value becomes equal to CCR0.
Output mode 7: PWM toggle/set mode:
The output is reset when the timer value becomes equal to
capture/compare data CCRx. It is set when the timer value
becomes equal to CCR0.