Texas Instruments MSP430x1xx - Manual (Page 28)

Introduction
2-2
2.1 Introduction
The architecture of the MSP430 family is based on a memory-to-memory
architecture, a common address space for all functional blocks, and a reduced
instruction set applicable to all functional blocks as illustrated in Figure 2–1.
See specific device data sheets for complete block diagrams of individual
devices.
Figure 2–1. MSP430 System Configuration
Oscillator
System
ACLK
MCLK
DATA I/O Port I/O Port I/O Port
CPU
Incl.
Bus
Conv.
Comparator USART USART Watchdog
MAB, 16 Bit
MDB, 16 Bit
MAB, 4 Bit
MDB, 8 Bit
R/W
Timer_B
Clock
Random
Logic
Module Select
PROGRAM
16 Reg.
2.2 Central Processing Unit
The CPU incorporates a reduced and highly transparent instruction set and a
highly orthogonal design. It consists of a 16-bit arithmetic logic unit (ALU), 16
registers, and instruction control logic. Four of these registers are used for
special purposes. These are the program counter (PC), stack pointer (SP),
status register (SR), and constant generator (CGx). All registers, except the
constant-generator registers R3/CG2 and part of R2/CG1, can be accessed
using the complete instruction set. The constant generator supplies instruction
constants, and is not used for data storage. The addressing mode used on
CG1 separates the data from the constants.
The CPU control over the program counter, the status register, and the stack
pointer (with the reduced instruction set) allows the development of
applications with sophisticated addressing modes and software algorithms.