Texas Instruments MSP430x1xx - Manual (Page 127)

Ports P1, P2
8-7
Digital I/O Configuration
Note: Function Select With P1SEL, P2SEL
The interrupt-edge-select circuitry is disabled if control bit PnSEL.x is set.
Therefore, the input signal can no longer generate an interrupt.
When a port pin is selected to be used as an input to a peripheral module other
than the I/O port (PnSEL.x = 1), the actual input signal to the peripheral module
is a latched representation of the signal at the device pin (see Figure 8–2
schematic). The latch uses the PnSEL.x bit as its enable, so while PnSEL.x=1,
the internal input signal simply follows the signal at the pin. However, if the
PnSEL.x bit is reset, then the output of the latch (and therefore the input to the
other peripheral module) represents the value of the signal at the device pin
just prior to the bit being reset.
8.2.2 Port P1, Port P2 Schematic
The pin logic of each individual port P1 and port P2 signal is identical. Each
bit can be read and written to as shown in Figure 8–2.
Figure 8–2. Schematic of One Bit in Port P1, P2
Pad Logic
Pn.x
Output
MUX
Output
MUX
Interrupt
Flag
Interrupt
Edge
Select
PnIE.x
PnIFG.x
PnIRQ.x
PnIRQ.y
PnIRQ.z
Request
Interrupt
Pn.07
PnSEL.x
PnIN.x
PnSEL.x
PnDIR.x
EN
A
Y
PnIES.x
Module x IN
Module X OUT
PnOUT.x
Direction Control
From Module
x = 0 to 7, according to bits 0 to 7
n = 1 for Port P1 and 2 for Port P2