Freescale Semiconductor MCF5480 - Manual (Page 1018)

MCF548x Reference Manual, Rev. 3
Index-4 Freescale Semiconductor
structure 21-19
time stamp 21-28
transmit
codes 21-22
error status flag (TXWARN) 21-16
priority 21-24
operation 21-19–21-31
bit timing configuration 21-29
debug mode 21-3
listen-only mode 21-4
receive process 21-24
registers
control (CANCTRL) 21-8
error and status (ESTAT) 21-15
interrupt flag (IFLAG) 21-18
interrupt mask (IMASK) 21-17
module configuration (CANMCR) 21-6
Rx 14 mask (RX14MASK) 21-13
Rx 15 Mask (RX15MASK) 21-13
Rx global mask (RXGMASK) 21-12
transmit process 21-23
FPU
data formats 3-17
floating-point 6-3
signed-integer 6-3
data types
denormalized numbers 6-5
infinities 6-4
normalized numbers 6-4
not-a-number 6-5
zeros 6-4
exceptions 6-17–6-23
BSUN 6-19
DZ 6-22
IDE 6-20
INAN 6-20
INEX 6-23
OPERR 6-21
OVFL 6-21
UNFL 6-22
instructions
execution timing 6-27
general 6-25
MC68000, differences 6-28
post-processing 6-14
conditional testing 6-15
overflow 6-14
round 6-14
underflow 6-14
registers
control (FPCR) 6-7
data (FPn) 6-7
instruction address (FPIAR) 6-10
status (FPSR) 6-9
results
intermediate 6-11
rounding 6-12
state frames 6-23
Frame reception, FlexCAN 21-24
Frame transmission, FlexCAN 21-23
G
GPIO
registers
DMA pin assignment (PAR_DMA) 15-23
DSPI pin assignment (PAR_DSPI) 15-30
FEC/I2C/IRQ pin assignment
(PAR_FECI2CIRQ) 15-23
FlexBus chip select pin assignment
(PAR_FBCS) 15-22
general purpose timer pin assignment
(PAR_TIMER) 15-31
PCI grant pin assignment (PAR_PCIBG) 15-25
PCI request pin assignment (PAR_PCIBR) 15-26
port clear output data (PCLRR_x) 15-18–15-20
port x data direction (PDDR_x) 15-11–15-14
port x output data (PODR_x) 15-8–15-11
port x pin assignment (PAR_x) 15-21
port x pin data/set data (PPDSDR_x) 15-14–15-17
PSC0 pin assignment (PAR_PSC0) 15-29
PSC1 pin assignment (PAR_PSC1) 15-28
PSC2 pin assignment (PAR_PSC2) 15-28
PSC3 pin assignment (PAR_PSC3) 15-27
signals 15-3–15-7
H
Hash table 30-49
I
I
2 C
acknowledge 28-10
block diagram 28-1
clock synchronization 28-11
data transfer 28-9
handshaking 28-12
initialization 28-12–28-18
memory map 28-3
registers
address (I2AR) 28-3
control (I2CR) 28-5
data I/O (I2DR) 28-7
frequency divider (I2FDR) 28-4
interrupt control (I2ICR) 28-7
status (I2SR) 28-5