Freescale Semiconductor MCF5480 - Manual (Page 1019)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor Index-5
repeated start 28-11
signals
SCL 28-2
SDA 28-2
START 28-9
STOP 28-9
Instructions
architecture additions 3-19
branch acceleration 3-4
debug 8-54, 8-60
EMAC
execution timing 4-11
summary 4-11
execution timing 3-27
branch 3-33
EMAC 3-34
FPU 3-35
miscellaneous 3-32
MOVE 3-28
one-operand 3-30
two-operand 3-31
fetch pipeline 3-3
JTAG
BYPASS 23-9
CLAMP 23-9
ENABLE_TEST_CTRL 23-9
EXTEST 23-8
HIGHZ 23-9
IDCODE 23-8
SAMPLE/PRELOAD 23-8
MOVEC 8-45
PULSE 8-6
STOP 8-7, 8-29
summary 3-22
WDDATA 8-6
Interrupt controller
features 13-1
interrupts
FlexCAN 21-31
prioritization 13-3
recognition 13-3
sources 13-12
vector determination 13-3
memory map 13-4
operation 13-1–13-3
registers
(IACKLPRn) 13-10
interrupt control (ICRnx) 13-11
interrupt force high/low (INTFRCHn,
INTFRCLn) 13-8
interrupt pending high/low (IPRHn, IPRLn) 13-5
interrupt request level (IRLRn) 13-10
level n IACK (LnIACK) 13-13
mask high/low (IMRHn, n) 13-7
software IACK (SWIACKR) 13-13
Interrupts
DSPI 27-31
PCI arbiter 20-10
PCI controller 19-70
processor 26-48
J
JTAG
instructions
BYPASS 23-9
CLAMP 23-9
ENABLE_TEST_CTRL 23-9
EXTEST 23-8
HIGHZ 23-9
IDCODE 23-8
SAMPLE/PRELOAD 23-8
low-power modes 23-9
memory map 23-4
operation
nonscan chain 23-9
registers
boundary scan 23-6
bypass 23-5
IDCODE 23-4
instruction shift (IR) 23-4
JTAG_CFM_CLKDIV 23-5
TEST_CTRL 23-5
signals
MTMOD0 23-2
test clock input (TCK) 23-3, 23-9
test data input/development serial input
(TDI/DSI) 23-3
test data output/development serial output
(TDO/DSO) 23-4
test mode select/breakpoint (TMS/BKPT) 23-3
test reset/development serial clock
(TRST/DSCLK) 23-4
TAP controller 23-6
L
Listen-only mode 21-4
Loop-back mode 21-4, 21-9
Low-power modes
JTAG 23-9
LURC 24-31
M
MAC, see EMAC
MBAR 3-13