Index – Freescale Semiconductor MCF5480 User Manual
Page 1015
Index
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
Index-1
A
Acknowledge error (ACKERR) 21-16
Addressing modes 3-18
Associated functions 15-3
B
BDM, see debug
Bit error (BITERR) 21-16
Bus off interrupt (BOFFINT) 21-17
Bus, see FlexBus 17-1
Byte lanes 17-2
C
Cache
cache-inhibited accesses 7-13
initialization 7-30
interaction with SRAM 7-1
line states 7-8
management 7-23
modes 7-12
copyback 7-13
write-through 7-12
protocol
read hit 7-15
read miss 7-14
write hit 7-15
write miss 7-14
registers
access control (ACRn) 3-13, 5-5, 5-6, 7-22
configuration (CACR) 3-13
control (CACR) 5-5, 7-19
Collision handling 30-53
Commands
BDM 8-33–8-50
SDRAM controller 18-10–18-13
Core
branch acceleration 3-4
enhancements 3-1
pipelines 3-2
instruction fetch 3-3
operand execution 3-4
registers
address (An) 3-9
condition code (CCR) 3-9
data (Dn) 3-9
module base address (MBAR) 3-13
RAM base address (RAMBAR) 3-13
status (SR) 3-12
user stack pointer (A7) 3-9
vector base (VBR) 3-12, 3-37
Crypto-channel 22-3, 22-11, 22-18
D
Debug
BDM
commands
DUMP 8-39
extension words 8-33
FILL 8-41
FORCE_TA 8-44
format 8-33
GO 8-42
NOP 8-43
RAREG/RDREG 8-35
RCREG 8-45
RDMREG 8-49
READ 8-36
summary 8-32
WAREG/WDREG 8-35
WCREG 8-48
WDMREG 8-50
WRITE 8-38
receive packet 8-30
serial interface 8-30
transmit packet 8-31
breakpoint operation theory 8-51
data breakpoint/mask registers 8-22
emulator mode 8-53
enhancements 3-6
instructions 8-54, 8-60
memory map 8-10
processor halted 8-8
processor stopped 8-7
real-time trace support 8-5–8-8
registers
address attribute (BAAR) 8-15
address breakpoint (ABLR, ABHR) 8-21
attribute trigger (AATR, AATR1) 8-16