Freescale Semiconductor MCF5480 - Manual (Page 1022)

MCF548x Reference Manual, Rev. 3
Index-8 Freescale Semiconductor
R
RAMBAR 3-13
Registers
cache
access control (ACRn) 3-13, 5-5, 5-6, 7-22
configuration (CACR) 3-13
control (CACR) 5-5, 7-19
core
address (An) 3-9
condition code (CCR) 3-9
data (Dn) 3-9
module base address (MBAR) 3-13
RAM base address (RAMBAR) 3-13
status (SR) 3-12
user stack pointer (A7) 3-9
vector base (VBR) 3-12, 3-37
debug
address attribute (BAAR) 8-15
address breakpoint (ABLR, ABHR) 8-21
attribute trigger (AATR, AATR1) 8-16
configuration/status (CSR) 8-11
data breakpoint/mask (DBR, DBMR) 8-22
extended trigger definition (XTDR) 8-25
PC breakpoint AISD (PBASID) 8-24
PC breakpoint ASID control (PBAC) 8-14
program counter breakpoint/mask (PBRn,
PBMR) 8-20
trigger definition (TDR) 8-17
DMA
current pointer (CP) 24-7
end pointer (EP) 24-8
external request address mask (EREQMASK) 24-21
external request base address (EREQBAR) 24-20
initiator mux control (IMCR) 24-13
initiator priority (IPRIORn) 24-12
interrupt mask (DIMR) 24-10
interrupt pending (DIPR) 24-10
PTD control (PTD) 24-9
task base address (TaskBAR) 24-6
task control (TCRn) 24-11
task size (TSKSZn 24-14
variable pointer (VP) 24-8
DSPI
clock and transfer attributes 0–7 (DCTARn) 27-7
DMA/interrupt request select (DIRSR) 27-13
module configuration (DMCR) 27-5
Rx FIFO (DRFR) 27-16
Rx FIFO debug 0–3 (DRFDRn) 27-17
status (DSR) 27-11
transfer count (DTCR) 27-7
Tx FIFO (DTFR) 27-15
Tx FIFO debug 0–3 (DTFDRn) 27-17
EMAC
mask (MASK) 4-10
status (MACSR) 4-5
EPORT
data direction (EPDDR) 14-3
flag (EPFR) 14-5
pin assignment (EPPAR) 14-3
pin data (EPPDR) 14-5
port data (EPDR) 14-4
port interrupt enable (EPIER) 14-4
Ethernet
control (ECR) 30-13
descriptor group lower address (GALR) 30-24
descriptor individual lower (IALR) 30-23
descriptor individual upper address (IAUR) 30-22
FEC transmit FIFO watermark (FECTFWR) 30-25
interrupt event (EIR) 30-10
interrupt mask (EIMR) 30-12
MIB control (MIBC) 30-17
MII management frame (MMFR) 30-14
MII speed control (MSCR) 30-15
opcode/pause duration (OPD) 30-22
physical address low (PALR) 30-20
receive control (RCR) 30-17
transmit control (TCR) 30-19
FlexBus
chip select address (CSARn) 17-8
chip select control (CSCRn) 17-10
chip select mask (CSMRn) 17-9
FlexCAN
control (CANCTRL) 21-8
error and status (ESTAT) 21-15
interrupt flag (IFLAG) 21-18
interrupt mask (IMASK) 21-17
module configuration (CANMCR) 21-6
Rx 14 mask (RX14MASK) 21-13
Rx 15 Mask (RX15MASK) 21-13
Rx global mask (RXGMASK) 21-12
FPU
control (FPCR) 6-7
data (FPn) 6-7
instruction address (FPIAR) 6-10
status (FPSR) 6-9
GPIO
DMA pin assignment (PAR_DMA) 15-23
DSPI pin assignment (PAR_DSPI) 15-30
FEC/I2C/IRQ pin assignment
(PAR_FECI2CIRQ) 15-23
FlexBus chip select pin assignment
(PAR_FBCS) 15-22
general purpose timer pin assignment
(PAR_TIMER) 15-31