Correctable internal error status register, Correctable internal error status register -34 – Altera Arria 10 Avalon-MM User Manual
Page 100
Bits
Register Description
Reset Value
Access
[6]
Mask for Corrected Internal Error reported by the Application
Layer.
1
RWS
[5]
Mask for configuration error detected in CvP mode.
0
RWS
[4:2]
Reserved.
0
RO
[1]
Mask for retry buffer correctable ECC error.
1
RWS
[0]
Mask for RX Buffer correctable ECC error.
1
RWS
Correctable Internal Error Status Register
Table 6-30: Correctable Internal Error Status Register
The
Correctable Internal Error Status
register reports the status of the internally checked errors that are
correctable. When these specific errors are enabled by the
Correctable Internal Error Mask
register, they are
forwarded as Correctable Internal Errors as defined in the PCI Express Base Specification 3.0. This register is for
debug only. It should only be used to observe behavior, not to drive logic custom logic.
Bits
Register Description
Reset Value
Access
[31:6]
Reserved.
0
RO
[5]
When set, indicates a configuration error has been detected in
CvP mode which is reported as correctable. This bit is set
whenever a
CVP_CONFIG_ERROR
occurs while in
CVP_MODE
.
0
RW1CS
[4:2]
Reserved.
0
RO
[1]
When set, the retry buffer correctable ECC error status indicates
an error.
0
RW1CS
[0]
When set, the RX buffer correctable ECC error status indicates an
error.
0
RW1CS
Related Information
6-34
Correctable Internal Error Status Register
UG-01145_avmm
2015.05.14
Altera Corporation
Registers