Altera Arria 10 Avalon-MM - Manual (Page 14)

Figure 1-2: PCI Express Application with a Single Root Port and Endpoint
The following figure shows a PCI Express link between two Arria 10 FPGAs.
Altera FPGA
User Application
Logic
PCIe
Hard IP
RP
PCIe
Hard IP
EP
User Application
Logic PCI Express Link
Altera FPGA
Figure 1-3: PCI Express Application Using Configuration via Protocol
The Arria 10 design below includes the following components:
• A Root Port that connects directly to a second FPGA that includes an Endpoint.
• Two Endpoints that connect to a PCIe switch.
• A host CPU that implements CvP using the PCI Express link connects through the switch. For more
information about configuration over a PCI Express link, refer to Configuration via Protocol (CvP)
on page 13-1.
1-8 Configurations
UG-01145_avmm
2015.05.14
Altera Corporation Datasheet
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