Altera Arria 10 Avalon-MM - Manual (Page 157)

these blocks to maximize interoperability with different variation files. The following table shows the
mapping.
Table 14-1: BAR Map
Memory BAR Mapping
32-bit BAR0
32-bit BAR1
64-bit BAR1:0 Maps to 32 KByte target memory block. Use the rc_slave module to bypass
the chaining DMA.
32-bit BAR2
32-bit BAR3
64-bit BAR3:2 Maps to DMA Read and DMA write control and status registers, a
minimum of 256 bytes.
32-bit BAR4
32-bit BAR5
64-bit BAR5:4 Maps to 32 KByte target memory block. Use the rc_slave module to bypass
the chaining DMA.
Expansion ROM BAR Not implemented by design example; behavior is unpredictable.
I/O Space BAR (any) Not implemented by design example; behavior is unpredictable.
Avalon-MM Test Driver Module
The BFM driver module, altpcietb_bfm_driver_avmm.v is configured to test the DMA example
Endpoint design. The BFM driver module configures the Endpoint Configuration Space registers and
then tests the example Endpoint DMA channel. This file is stored in the <variation_name>_tb/altera_pcie_
<dev>>_tbed_<quartus_ver>/sim/ directory.
The BFM test driver module performs the following steps in sequence:
1. Configures the Root Port and Endpoint Configuration Spaces, which the BFM test driver module does
by calling the procedure
ebfm_cfg_rp_ep
, which is part of altpcietb_bfm_configure.
2. Finds a suitable BAR to access the example Endpoint design Control Register space. Either BARs 2 or 3
must be at least a 256-byte memory BAR to perform the DMA channel test. The
find_mem_bar
procedure in the altpcietb_bfm_driver_avmm does this.
3. If a suitable BAR is found in the previous step, the driver performs the following tasks:
a. DMA read—The driver programs the DMA to read data from the BFM shared memory into the
Endpoint memory. The descriptor control fields specify for the DMA to issue an MSI when the last
descriptor has completed.
a. DMA write—The driver programs the DMA to write the data from its Endpoint memory back to
the BFM shared memory. The descriptor control fields are specified so that the DMA completes the
following steps to indicate transfer completion:
UG-01145_avmm
2015.05.14
Avalon-MM Test Driver Module 14-7
Avalon-MM Testbench and Design Example Altera Corporation
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