Enabling MSI or Legacy Interrupts .......................................................................................................... 8-2
Generation of Avalon-MM Interrupts .....................................................................................................8-3
Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
...................................................................................................................................................................8-3
Error Handling ................................................................................................... 9-1
Physical Layer Errors ..................................................................................................................................9-2
Data Link Layer Errors ...............................................................................................................................9-2
Transaction Layer Errors ........................................................................................................................... 9-3
Error Reporting and Data Poisoning ....................................................................................................... 9-6
Uncorrectable and Correctable Error Status Bits ...................................................................................9-7
IP Core Architecture......................................................................................... 10-1
Top-Level Interfaces .................................................................................................................................10-3
Avalon-MM Interface............................................................................................................................... 10-3
Clocks and Reset ....................................................................................................................................... 10-3
Interrupts ................................................................................................................................................... 10-3
PIPE ............................................................................................................................................................ 10-3
Data Link Layer .........................................................................................................................................10-4
Physical Layer ............................................................................................................................................10-6
32-Bit PCI Express Avalon-MM Bridge ................................................................................................ 10-8
Avalon-MM Bridge TLPs .......................................................................................................... 10-11
Avalon-MM-to-PCI Express Write Requests ......................................................................... 10-11
Avalon-MM-to-PCI Express Upstream Read Requests ........................................................10-11
PCI Express-to-Avalon-MM Read Completions ................................................................... 10-12
PCI Express-to-Avalon-MM Downstream Write Requests ................................................. 10-12
PCI Express-to-Avalon-MM Downstream Read Requests ...................................................10-12
Avalon-MM-to-PCI Express Read Completions ................................................................... 10-13
PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge ..................................10-13
Minimizing BAR Sizes and the PCIe Address Space ............................................................. 10-15
Avalon-MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing ......10-17
Completer Only Single Dword Endpoint ............................................................................................10-19
RX Block .......................................................................................................................................10-20
Avalon-MM RX Master Block .................................................................................................. 10-20
TX Block .......................................................................................................................................10-21
Interrupt Handler Block ............................................................................................................ 10-21
Design Implementation.................................................................................... 11-1
Making Pin Assignments to Assign I/O Standard to Serial Data Pins ..............................................11-1
Recommended Reset Sequence to Avoid Link Training Issues ......................................................... 11-1
SDC Timing Constraints.......................................................................................................................... 11-2
Throughput Optimization................................................................................ 12-1
Throughput of Posted Writes ................................................................................................................. 12-3
Throughput of Non-Posted Reads ......................................................................................................... 12-3
TOC-4
Altera Corporation
