Altera Arria 10 Avalon-MM - Manual (Page 155)

Note: The DMA design example requires setting BAR 2 or BAR 3 to a minimum of 256 bytes. To run the
DMA tests using MSI, you must set the Number of MSI messages requested parameter under the
PCI Express/PCI Capabilities page to at least 2.
The DMA design example uses an architecture capable of transferring a large amount of fragmented
memory without accessing the DMA registers for every memory block. For each block of memory to be
transferred, the DMA design example uses a descriptor table containing the following information:
• Length of the transfer
• Address of the source
• Address of the destination
• Control bits to set the handshaking behavior between the software application or BFM driver and the
DMA module
Note: The DMA design example only supports dword-aligned accesses. The DMA design example does
not support ECRC forwarding.
The BFM driver writes the descriptor tables into BFM shared memory, from which the DMA design
engine continuously collects the descriptor tables for DMA read, DMA write, or both. At the beginning of
the transfer, the BFM programs the Endpoint DMA control register. The DMA control register indicates
the total number of descriptor tables and the BFM shared memory address of the first descriptor table.
After programming the DMA control register, the DMA engine continuously fetches descriptors from the
BFM shared memory for both DMA reads and DMA writes, and then performs the data transfer for each
descriptor.
The following figure shows a block diagram of the design example connected to an external RC CPU.
Figure 14-2: Top-Level DMA Example for Simulation
Root Complex
CPU
Root Port
Memory
Write
Descriptor
Table
Data
User Application DMA
Endpoint Memory
Avalon-MM
interfaces
Arria 10 Hard IP
for PCI Express
DMA Controller Core
DMA Read
Avalon-MM
PCI Express
DMA Write
RC Slave
Read
Descriptor
Table
UG-01145_avmm
2015.05.14
Endpoint Design Example 14-5
Avalon-MM Testbench and Design Example Altera Corporation
Send Feedback