Altera Arria 10 Avalon-MM - Manual (Page 167)

The
ebfm_cfg_rp_ep
executes the following steps to initialize the Configuration Space:
1. Sets the Root Port Configuration Space to enable the Root Port to send transactions on the PCI
Express link.
2. Sets the Root Port and Endpoint PCI Express Capability Device Control registers as follows:
a. Disables
Error Reporting
in both the Root Port and Endpoint. BFM does not have error handling
capability.
b. Enables
Relaxed Ordering
in both Root Port and Endpoint.
c. Enables
Extended Tags
for the Endpoint, if the Endpoint has that capability.
d. Disables
Phantom Functions
,
Aux Power PM
, and
No Snoop
in both the Root Port and Endpoint.
e. Sets the
Max Payload Size
to what the Endpoint supports because the Root Port supports the
maximum payload size.
f. Sets the Root Port
Max Read Request Size
to 4 KBytes because the example Endpoint design
supports breaking the read into as many completions as necessary.
g. Sets the Endpoint
Max Read Request Size
equal to the
Max Payload Size
because the Root Port
does not support breaking the read request into multiple completions.
3. Assigns values to all the Endpoint BAR registers. The BAR addresses are assigned by the algorithm
outlined below.
a. I/O BARs are assigned smallest to largest starting just above the ending address of BFM shared
memory in I/O space and continuing as needed throughout a full 32-bit I/O space.
b. The 32-bit non-prefetchable memory BARs are assigned smallest to largest, starting just above the
ending address of BFM shared memory in memory space and continuing as needed throughout a
full 32-bit memory space.
c. Assignment of the 32-bit prefetchable and 64-bit prefetchable memory BARS are based on the value
of the
addr_map_4GB_limit
input to the
ebfm_cfg_rp_ep.
The default value of the
addr_map_4GB_limit
is
0
.
If the
addr_map_4GB_limit
input to the
ebfm_cfg_rp_ep
is set to 0, then the 32-bit prefetchable
memory BARs are assigned largest to smallest, starting at the top of 32-bit memory space and
continuing as needed down to the ending address of the last 32-bit non-prefetchable BAR.
However, if the
addr_map_4GB_limit
input is set to 1, the address map is limited to 4 GByte, the
32-bit and 64-bit prefetchable memory BARs are assigned largest to smallest, starting at the top of
the 32-bit memory space and continuing as needed down to the ending address of the last 32-bit
non-prefetchable BAR.
d. If the
addr_map_4GB_limit
input to the
ebfm_cfg_rp_ep
is set to 0, then the 64-bit prefetchable
memory BARs are assigned smallest to largest starting at the 4 GByte address assigning memory
ascending above the 4 GByte limit throughout the full 64-bit memory space.
If the
addr_map_4 GB_limit
input to the
ebfm_cfg_rp_ep
is set to 1, then the 32-bit and the 64-bit
prefetchable memory BARs are assigned largest to smallest starting at the 4 GByte address and
assigning memory by descending below the 4 GByte address to addresses memory as needed down
to the ending address of the last 32-bit non-prefetchable BAR.
The above algorithm cannot always assign values to all BARs when there are a few very large (1
GByte or greater) 32-bit BARs. Although assigning addresses to all BARs may be possible, a more
complex algorithm would be required to effectively assign these addresses. However, such a
UG-01145_avmm
2015.05.14
Configuration of Root Port and Endpoint 14-17
Avalon-MM Testbench and Design Example Altera Corporation
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