Altera Arria 10 Avalon-MM - Manual (Page 109)

Generation of Avalon-MM Interrupts
The generation of Avalon-MM interrupts requires the instantiation of the CRA slave module where the
interrupt registers and control logic are implemented. The CRA slave port has an Avalon-MM Interrupt
output signal,
cra_Irq_irq
. A write access to an Avalon-MM mailbox register sets one of the
P2A_MAILBOX_INT<n>
bits in the
Avalon-MM to PCI Express Interrupt Status Register
and asserts
the
cra_Irq_o
or
cra_Irq_irq
output, if enabled. Software can enable the interrupt by writing to the
INT_X Interrupt Enable Register for Endpoints
through the CRA slave. After servicing the
interrupt, software must clear the appropriate serviced interrupt
status
bit in the PCI-Express-to-
Avalon-MM
Interrupt Status
register and ensure that no other interrupt is pending.
Related Information
• Avalon-MM to PCI Express Interrupt Status Registers on page 6-15
• PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints on page 6-19
Interrupts for Endpoints Using the Avalon-MM Interface with Multiple
MSI/MSI-X Support
If you select Enable multiple MSI/MSI X support under the Avalon-MM System Settings banner in the
parameter editor, the Hard IP for PCI Express exports the MSI, MSI-X, and INTx interfaces to the
Application Layer. The Application Layer must include a Custom Interrupt Handler to send interrupts to
the Root Port. You must design this Custom Interrupt Handler. The following figure provides an
overview of the logic for the Custom Interrupt Handler. The Custom Interrupt Handler should include
hardware to perform the following tasks:
• An MSI/MXI-X IRQ Avalon-MM Master port to drive MSI or MSI-X interrupts as memory writes to
the PCIe Avalon-MM bridge.
• A legacy interrupt signal,
IntxReq_i
, to drive legacy interrupts from the MSI/MSI-X IRQ module to
the Hard IP for PCI Express.
• An MSI/MSI-X Avalon-MM Slave port to receive interrupt control and status from the PCIe Root
Port.
• An MSI-X table to store the MSI-X table entries. The PCIe Root Port sets up this table.
UG-01145_avmm
2015.05.14
Generation of Avalon-MM Interrupts 8-3
Interrupts for Endpoints Altera Corporation
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