Altera Arria 10 Avalon-MM User Manual
Page 78
Bits
Register Description
Reset Value
Access
[1]
HIP_CLK_SEL
. Selects between PMA and fabric clock when
USER_
MODE
= 1 and
PLD_CORE_READY
= 1. The following encodings are
defined:
• 1: Selects internal clock from PMA which is required for
CVP_
MODE
.
• 0: Selects the clock from soft logic fabric. This setting should
only be used when the fabric is configured in
USER_MODE
with
a configuration file that connects the correct clock.
To ensure that there is no clock switching during CvP, you should
only change this value when the Hard IP for PCI Express has been
idle for 10 µs and wait 10 µs after changing this value before
resuming activity.
1’b0
RW
[0]
CVP_MODE
. Controls whether the IP core is in
CVP_MODE
or normal
mode. The following encodings are defined:
• 1:
CVP_MODE
is active. Signals to the FPGA control block active
and all TLPs are routed to the Configuration Space. This
CVP_
MODE
cannot be enabled if
CVP_EN
= 0.
• 0: The IP core is in normal mode and TLPs are routed to the
FPGA fabric.
1’b0
RW
Table 6-9: CvP Data Registers
The following table defines the
CvP Data
registers. For 64-bit data, the optional
CvP Data2
stores the upper 32
bits of data. Programming software should write the configuration data to these registers. If you Every write to
these register sets the data output to the FPGA control block and generates <n> clock cycles to the FPGA control
block as specified by the
CVP_NUM_CLKS
field in the
CvP Mode
Control
register. Software must ensure that all bytes
in the memory write dword are enabled. You can access this register using configuration writes, alternatively,
when in CvP mode, these registers can also be written by a memory write to any address defined by a memory
space BAR for this device. Using memory writes should allow for higher throughput than configuration writes.
Bits
Register Description
Reset Value
Access
[31:0]
Upper 32 bits of configuration data to be transferred to the FPGA
control block to configure the device. You can choose 32- or 64-
bit data.
0x00000000
RW
[31:0]
Lower 32 bits of configuration data to be transferred to the FPGA
control block to configure the device.
0x00000000
RW
Table 6-10: CvP Programming Control Register
This register is written by the programming software to control CvP programming.
Bits
Register Description
Reset Value
Access
[31:2]
Reserved.
0x0000
RO
6-12
CvP Registers
UG-01145_avmm
2015.05.14
Altera Corporation
Registers