Altera Arria 10 Avalon-MM - Manual (Page 41)

Figure 4-2: Arria 10 Devices with 72 Transceiver Channels and Four PCIe Hard IP Blocks
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
PCIe
Gen3
Hard IP
(with CvP)
PCIe
Gen3
Hard IP
PCIe
Gen3
Hard IP
GT 115 SF45
GT 090 SF45
GXBL1C
GXBL1D
GXBL1E
GXBL1F
GXBL1G
GXBL1H
GXBL1C
GXBL1E
GXBL1F
GXBL1G
GXBL1H
GXBR4D GXBR4D
GXBR4E GXBR4E
GXBR4F GXBR4F
GXBR4G GXBR4G
GXBR4H GXBR4H
GXBR4I GXBR4I
Notes:
(1) Nomenclature of left column bottom transceiver banks always begins with “C”
(2) Nomenclature of right column bottom transceiver banks may begin with “C”, “D”, or “E”.
(1) (2)
GXBL1D
4-2 Physical Layout of Hard IP In Arria 10 Devices
UG-01145_avmm
2015.05.14
Altera Corporation Physical Layout of Hard IP In Arria 10 Devices
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