Altera Arria 10 Avalon-MM User Manual
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This design is consuming 1.25 GB of PCIe address space when only 276 MBytes are actually required. The
solution is to edit the address map to place the base address of each BAR at 0x0000_0000. The following
figure illustrates the optimized address map.
Figure 10-8: Optimized Address Map
Figure 10-9: Reduced Address Bits for BAR2 and BAR4
The following figure shows the number of address bits required when the smaller memories accessed by
BAR2 and BAR4 have a base address of 0x0000_0000.
For cases where the BAR Avalon-MM RX master port connects to more than one Avalon-MM slave,
assign the base addresses of the slaves sequentially and place the slaves in the smallest power-of-two-sized
address space possible. Doing so minimizes the system address space used by the BAR.
Related Information
Avalon-MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
Note: The PCI Express-to-Avalon-MM bridge supports both 32- and 64-bit addresses. If you select 64-bit
addressing the bridge does not perform address translation.
When you specify 32-bit addresses, the Avalon-MM address of a received request on the TX Avalon-MM
slave port is translated to the PCI Express address before the request packet is sent to the Transaction
Layer. You can specify up to 512 address pages and sizes ranging from 4 KByte to 4 GBytes when you
customize your Avalon-MM Arria 10 Hard IP for PCI Express as described in Avalon to PCIe Address
Translation Settings . This address translation process proceeds by replacing the MSB of the Avalon-MM
address with the value from a specific translation table entry; the LSB remains unchanged. The number of
MSBs to be replaced is calculated based on the total address space of the upstream PCI Express devices
that the Avalon-MM Hard IP for PCI Express can access. The number of MSB bits is defined by the
difference between the maximum number of bits required to represent the address space supported by the
upstream PCI Express device minus the number of bits required to represent the Size of address pages
which are the LSB pass-through bits (N). The Size of address pages (N) is applied to all entries in the
translation table.
Each of the 512 possible entries corresponds to the base address of a PCI Express memory segment of a
specific size. The segment size of each entry must be identical. The total size of all the memory segments is
used to determine the number of address MSB to be replaced. In addition, each entry has a 2-bit field,
UG-01145_avmm
2015.05.14
Avalon-MM-to-PCI Express Address Translation Algorithm for 32-Bit...
10-17
IP Core Architecture
Altera Corporation