Altera Arria 10 Avalon-MM - Manual (Page 84)

Address Name Access Description
0x0904
A2P_MAILBOX1
RO Avalon-MM-to-PCI Express Mailbox 1
0x0908
A2P_MAILBOX2
RO Avalon-MM-to-PCI Express Mailbox 2
0x090C
A2P_MAILBOX3
RO Avalon-MM-to-PCI Express Mailbox 3
0x0910
A2P_MAILBOX4
RO Avalon-MM-to-PCI Express Mailbox 4
0x0914
A2P_MAILBOX5
RO Avalon-MM-to-PCI Express Mailbox 5
0x0918
A2P_MAILBOX6
RO Avalon-MM-to-PCI Express Mailbox 6
0x091C
A2P_MAILBOX7
RO Avalon-MM-to-PCI Express Mailbox 7
Avalon-MM-to-PCI Express Address Translation Table
The Avalon-MM-to-PCI Express address translation table is writable using the CRA slave port. Each
entry in the PCI Express address translation table is 8 bytes wide, regardless of the value in the current
PCI Express address width parameter. Therefore, register addresses are always the same width, regardless
of PCI Express address width.
These table entries are repeated for each address specified in the Number of address pages parameter. If
Number of address pages is set to the maximum of 512, 0x1FF8 contains A2P_ADDR_SPACE511 and
A2P_ADDR_MAP_LO511 and 0x1FFC contains A2P_ADDR_MAP_HI511.
Table 6-18: Avalon-MM-to-PCI Express Address Translation Table, 0x1000–0x1FFF
Address Bits Name Access Description
0x1000
[1:0] A2P_ADDR_
SPACE0
RW Address space indication for entry 0. The following
encodings are defined:
• 2’b00:. Memory Space, 32-bit PCI Express address.
32-bit header is generated. Address bits 63:32 of the
translation table entries are ignored.
• 2’b01: Memory space, 64-bit PCI Express address.
64-bit address header is generated.
• 2’b10: Reserved
• 2’b11: Reserved
[31:2] A2P_ADDR_
MAP_LO0
RW Lower bits of Avalon-MM-to-PCI Express address map
entry 0.
0x1004 [31:0] A2P_ADDR_
MAP_HI0
RW Upper bits of Avalon-MM-to-PCI Express address map
entry 0.
6-18 Avalon-MM-to-PCI Express Address Translation Table
UG-01145_avmm
2015.05.14
Altera Corporation Registers
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