Altera Arria 10 Avalon-MM User Manual
Page 48
64- or 128-Bit Avalon-MM Interface to the
Application Layer
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2015.05.14
UG-01145_avmm
This chapter describes the top-level signals of the Arria 10 Hard IP for PCI Express using the Avalon-MM
interface to the Application Layer. The Avalon-MM bridge translates PCI Express read, write and
completion TLPs into standard Avalon-MM read and write commands for the Avalon-MM RX Master
Port interface. For the Avalon-MM TX Slave Port interface, the bridge translates Avalon-MM reads and
writes into PCI Express TLPs. The Avalon-MM read and write commands are the same as those used by
master and slave interfaces to access memories and registers. Consequently, you do not need a detailed
understanding of the PCI Express TLPs to use this Avalon-MM variant.
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