Correctable internal error mask register, Correctable internal error mask register -33 – Altera Arria 10 Avalon-MM User Manual
Page 99
Bits
Register Description
Reset
Value
Access
[10]
Reserved.
0
RO
[9]
When set, indicates a parity error was detected on the Configu‐
ration Space to TX bus interface
0
RW1CS
[8]
When set, indicates a parity error was detected on the TX to
Configuration Space bus interface
0
RW1CS
[7]
When set, indicates a parity error was detected in a TX TLP and
the TLP is not sent.
0
RW1CS
[6]
When set, indicates that the Application Layer has detected an
uncorrectable internal error.
0
RW1CS
[5]
When set, indicates a configuration error has been detected in
CvP mode which is reported as uncorrectable. This bit is set
whenever a
CVP_CONFIG_ERROR
rises while in
CVP_MODE
.
0
RW1CS
[4]
When set, indicates a parity error was detected by the TX Data
Link Layer.
0
RW1CS
[3]
When set, indicates a parity error has been detected on the RX
to Configuration Space bus interface.
0
RW1CS
[2]
When set, indicates a parity error was detected at input to the
RX Buffer.
0
RW1CS
[1]
When set, indicates a retry buffer uncorrectable ECC error.
0
RW1CS
[0]
When set, indicates a RX buffer uncorrectable ECC error.
0
RW1CS
Related Information
Correctable Internal Error Mask Register
Table 6-29: Correctable Internal Error Mask Register
The
Correctab
le Internal Error Mask
register controls which errors are forwarded as Internal Correctable
Errors. This register is for debug only.
Bits
Register Description
Reset Value
Access
[31:7]
Reserved.
0
RO
UG-01145_avmm
2015.05.14
Correctable Internal Error Mask Register
6-33
Registers
Altera Corporation