Altera Arria 10 Avalon-MM - Manual (Page 127)

The Avalon-MM bridge provides three possible Avalon-MM ports: a bursting master, an optional
bursting slave, and an optional non-bursting slave. The Avalon-MM bridge comprises the following three
modules:
• TX Slave Module—This optional 64- or 128-bit bursting, Avalon-MM dynamic addressing slave port
propagates read and write requests of up to 4 KBytes in size from the interconnect fabric to the PCI
Express link. The bridge translates requests from the interconnect fabric to PCI Express request
packets.
• RX Master Module—This 64- or 128-bit bursting Avalon-MM master port propagates PCI Express
requests, converting them to bursting read or write requests to the interconnect fabric.
• Control Register Access (CRA) Slave Module—This optional, 32-bit Avalon-MM dynamic addressing
slave port provides access to internal control and status registers from upstream PCI Express devices
and external Avalon-MM masters. Implementations that use MSI or dynamic address translation
require this port. The CRA port supports single dword read and write requests. It does not support
bursting.
When you select the Single dword completer for the Avalon-MM Hard IP for PCI Express, Qsys
substitutes a unpipelined, 32-bit RX master port for the 64- or 128-bit full-featured RX master port. The
following figure shows the block diagram of a full-featured PCI Express Avalon-MM bridge.
UG-01145_avmm
2015.05.14
32-Bit PCI Express Avalon-MM Bridge 10-9
IP Core Architecture Altera Corporation
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