Altera Arria 10 Avalon-MM - Manual (Page 5)

Optional Features..............................................................................................13-1
Configuration via Protocol (CvP) .......................................................................................................... 13-1
ECRC .......................................................................................................................................................... 13-2
ECRC on the RX Path .................................................................................................................. 13-2
ECRC on the TX Path .................................................................................................................. 13-3
Avalon-MM Testbench and Design Example .................................................. 14-1
Arria 10 Avalon-MM Endpoint Testbench ...........................................................................................14-2
Arria 10 Avalon-MM Root Port Testbench .......................................................................................... 14-4
Endpoint Design Example........................................................................................................................14-4
BAR/Address Map ........................................................................................................................14-6
Avalon-MM Test Driver Module ........................................................................................................... 14-7
DMA Write Cycles ................................................................................................................................... 14-8
DMA Read Cycles ...................................................................................................................................14-10
Avalon-MM Root Port Design Example ............................................................................................. 14-12
Root Port BFM ........................................................................................................................................ 14-14
BFM Memory Map .....................................................................................................................14-16
Configuration Space Bus and Device Numbering ................................................................. 14-16
Configuration of Root Port and Endpoint ..............................................................................14-16
Issuing Read and Write Transactions to the Application Layer .......................................... 14-21
BFM Procedures and Functions ........................................................................................................... 14-22
ebfm_barwr Procedure .............................................................................................................. 14-22
ebfm_barwr_imm Procedure ....................................................................................................14-23
ebfm_barrd_wait Procedure ..................................................................................................... 14-24
ebfm_barrd_nowt Procedure ....................................................................................................14-25
ebfm_cfgwr_imm_wait Procedure ...........................................................................................14-26
ebfm_cfgwr_imm_nowt Procedure ......................................................................................... 14-26
ebfm_cfgrd_wait Procedure ......................................................................................................14-27
ebfm_cfgrd_nowt Procedure .....................................................................................................14-28
BFM Configuration Procedures................................................................................................ 14-29
BFM Shared Memory Access Procedures ............................................................................... 14-31
BFM Log and Message Procedures .......................................................................................... 14-34
Verilog HDL Formatting Functions ........................................................................................ 14-38
Procedures and Functions Specific to the Chaining DMA Design Example...................... 14-42
Setting Up Simulation.............................................................................................................................14-49
Changing Between Serial and PIPE Simulation ..................................................................... 14-49
Using the PIPE Interface for Gen1 and Gen2 Variants .........................................................14-49
Viewing the Important PIPE Interface Signals........................................................................14-49
Disabling the Scrambler for Gen1 and Gen2 Simulations .................................................... 14-49
Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations.....................14-50
Debugging .........................................................................................................15-1
Simulation Fails To Progress Beyond Polling.Active State..................................................................15-1
Hardware Bring-Up Issues ...................................................................................................................... 15-1
Link Training .............................................................................................................................................15-2
TOC-5
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