Altera Arria 10 Avalon-MM - Manual (Page 102)

Reset Sequence for Hard IP for PCI Express IP Core and Application Layer
Figure 7-2: Hard IP for PCI Express and Application Logic Reset Sequence
Your Application Layer can instantiate a module similar to the one in this figure to generate
app_rstn
,
which resets the Application Layer logic.
pin_perst
pld_clk_inuse
serdes_pll_locked
crst
32 cycles
32 cycles
srst
reset_status
app_rstn
This reset sequence includes the following steps:
1. After
pin_perst
or
npor
is released, the Hard IP reset controller waits for
pld_clk_inuse
to be
asserted.
2.
csrt
and
srst
are released 32 cycles after
pld_clk_inuse
is asserted.
3. The Hard IP for PCI Express deasserts the
reset_status
output to the Application Layer.
4. The altpcied_<device>v_hwtcl.sv deasserts
app_rstn
32
pld_clk
cycles after
reset_status
is released.
7-2 Reset Sequence for Hard IP for PCI Express IP Core and Application Layer
UG-01145_avmm
2015.05.14
Altera Corporation Arria 10 Reset and Clocks
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