Ip core architecture, Ip core architecture -1 – Altera Arria 10 Avalon-MM User Manual
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IP Core Architecture
10
2015.05.14
UG-01145_avmm
The Avalon-MM Arria 10 Hard IP for PCI Express implements the complete PCI Express protocol stack
as defined in the PCI Express Base Specification. The protocol stack includes the following layers:
• Transaction Layer—The Transaction Layer contains the Configuration Space, which manages
communication with the Application Layer, the RX and TX channels, the RX buffer, and flow control
credits.
• Data Link Layer—The Data Link Layer, located between the Physical Layer and the Transaction Layer,
manages packet transmission and maintains data integrity at the link level. Specifically, the Data Link
Layer performs the following tasks:
• Manages transmission and reception of Data Link Layer Packets (DLLPs)
• Generates all transmission cyclical redundancy code (CRC) values and checks all CRCs during
reception
• Manages the retry buffer and retry mechanism according to received ACK/NAK Data Link Layer
packets
• Initializes the flow control mechanism for DLLPs and routes flow control credits to and from the
Transaction Layer
• Physical Layer—The Physical Layer initializes the speed, lane numbering, and lane width of the PCI
Express link according to packets received from the link and directives received from higher layers.
The following figure provides a high-level block diagram.
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