Altera Arria 10 Avalon-MM - Manual (Page 126)

The PHYMAC block comprises four main sub-blocks:
• MAC Lane—Both the RX and the TX path use this block.
• On the RX side, the block decodes the Physical Layer packet and reports to the LTSSM the type and
number of TS1/TS2 ordered sets received.
• On the TX side, the block multiplexes data from the DLL and the LTSTX sub-block. It also adds
lane specific information, including the lane number and the force PAD value when the LTSSM
disables the lane during initialization.
• LTSSM—This block implements the LTSSM and logic that tracks TX and RX data on each lane.
• For transmission, it interacts with each MAC lane sub-block and with the LTSTX sub-block by
asserting both global and per-lane control bits to generate specific Physical Layer packets.
• On the receive path, it receives the Physical Layer packets reported by each MAC lane sub-block. It
also enables the multilane deskew block. This block reports the Physical Layer status to higher
layers.
• LTSTX (Ordered Set and SKP Generation)—This sub-block generates the Physical Layer packet. It
receives control signals from the LTSSM block and generates Physical Layer packet for each lane. It
generates the same Physical Layer Packet for all lanes and PAD symbols for the link or lane number
in the corresponding TS1/TS2 fields.
The block also handles the receiver detection operation to the PCS sub-layer by asserting predefined PIPE
signals and waiting for the result. It also generates a SKP Ordered Set at every predefined timeslot and
interacts with the TX alignment block to prevent the insertion of a SKP Ordered Set in the middle of
packet.
• Deskew—This sub-block performs the multilane deskew function and the RX alignment between the
number of initialized lanes and the 64-bit data path.
The multilane deskew implements an eight-word FIFO buffer for each lane to store symbols. Each symbol
includes eight data bits, one disparity bit, and one control bit. The FIFO discards the FTS, COM, and SKP
symbols and replaces PAD and IDL with D0.0 data. When all eight FIFOs contain data, a read can occur.
When the multilane lane deskew block is first enabled, each FIFO begins writing after the first COM is
detected. If all lanes have not detected a COM symbol after seven clock cycles, they are reset and the
resynchronization process restarts, or else the RX alignment function recreates a 64-bit data word which is
sent to the DLL.
32-Bit PCI Express Avalon-MM Bridge
The Avalon-MM Arria 10 Hard IP for PCI Express includes an Avalon-MM bridge module that connects
the Hard IP to the interconnect fabric. The bridge facilitates the design of Endpoints and Root Ports that
include Qsys components.
10-8 32-Bit PCI Express Avalon-MM Bridge
UG-01145_avmm
2015.05.14
Altera Corporation IP Core Architecture
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