Altera Arria 10 Avalon-MM - Manual (Page 154)

Arria 10 Avalon-MM Root Port Testbench
This testbench simulates up to an ×8 PCI Express link using either the PIPE interfaces or the serial PCI
Express interface of the Root Port and Endpoints. The testbench design does not allow more than one PCI
Express link to be simulated at a time. The top-level of the testbench instantiates four main modules:
• <qsys_systemname>— Name of Root Port This is the example Root Port design. For more information
about this module, refer to Root Port Design Example.
• altpcietb_bfm_ep_example_chaining_pipen1b—This is the Endpoint PCI Express mode described in
the section DMA Design Examples.
• altpcietb_pipe_phy—There are eight instances of this module, one per lane. These modules connect
the PIPE MAC layer interfaces of the Root Port and the Endpoint. The module mimics the behavior of
the PIPE PHY layer to both MAC interfaces.
• altpcietb_bfm_driver_rp—This module drives transactions to the Root Port BFM. This is the module
that you modify to vary the transactions sent to the example Endpoint design or your own design. For
more information about this module, see Test Driver Module.
The testbench has routines that perform the following tasks:
• Generates the reference clock for the Endpoint at the required frequency.
• Provides a reset at start up.
Note: Before running the testbench, you should set the following parameters:
•
serial_sim_hwtcl
: Set this parameter in <instantiation name>_tb.v . This parameter controls
whether the testbench simulates in PIPE mode or serial mode. When is set to 0, the simulation
runs in PIPE mode; when set to 1, it runs in serial mode. Although the
serial_sim_hwtcl
parameter is available in other files, if you set this parameter at the lower level, then it will get
overwritten by the tb.v level.
•
serial_sim_hwtcl
: Set to 1 for serial simulation and 0 for PIPE simulation.
•
enable_pipe32_sim_hwtcl
: Set to 0 for serial simulation and 1 for PIPE simulation.
Endpoint Design Example
This design example comprises native Endpoint, a DMA application and a Root Port. The write DMA
module implements write operations from the Endpoint memory to the root complex (RC) memory. The
read DMA implements read operations from the RC memory to the Endpoint memory. The DMA and
Endpoint support simultaneous read and write transactions.
When operating on a hardware platform, the DMA is typically controlled by a software application
running on the root complex processor. In simulation, the generated testbench, along with this design
example, provides a BFM driver module in Verilog HDL that controls the DMA operations. Because the
example relies on no other hardware interface than the PCI Express link, you can use the design example
for the initial hardware validation of your system.
The end point or Root Port variant is generated in the language (Verilog HDL or VHDL) that you selected
for the variation file. The testbench files are only generated in Verilog HDL in the current release. If you
choose to use VHDL for your variant, you must have a mixed-language simulator to run this testbench.
14-4 Arria 10 Avalon-MM Root Port Testbench
UG-01145_avmm
2015.05.14
Altera Corporation Avalon-MM Testbench and Design Example
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