Altera Arria 10 Avalon-MM - Manual (Page 108)

Figure 8-1: Avalon-MM Interrupt Propagation to the PCI Express Link
Interrupt Disable
(Configuration Space Command Register [10])
Avalon-MM-to-PCI-Express
Interrupt Status and Interrupt
Enable Register Bits
A2P_MAILBOX_INT7 (enable)
A2P_MB_IRQ7 (request)
A2P_MAILBOX_INT6 (enable)
A2P_MB_IRQ6 (request)
A2P_MAILBOX_INT5 (enable)
A2P_MB_IRQ5 (request)
A2P_MAILBOX_INT4 (enable)
A2P_MB_IRQ4(request)
A2P_MAILBOX_INT3 (enable)
A2P_MB_IRQ3 (request)
A2P_MAILBOX_INT2 (enable)
A2P_MB_IRQ2 (request)
A2P_MAILBOX_INT1 (enable)
A2P_MB_IRQ1 (request)
A2P_MAILBOX_INT0 (enable)
A2P_MB_IRQ0 (request)
AV_IRQ_ASSERTED
AVL_IRQ
Q
Q
CLR
SET
D
MSI Enable
(Configuration Space Message Control Register[0])
MSI Request
PCI Express Virtual INTA signalling
(When signal rises ASSERT_INTA Message Sent)
(When signal falls DEASSERT_INTA Message Sent)
Related Information
• Avalon-MM to PCI Express Interrupt Enable Registers on page 6-16
• Avalon-MM to PCI Express Interrupt Status Registers on page 6-15
Enabling MSI or Legacy Interrupts
The PCI Express Avalon-MM bridge selects either MSI or legacy interrupts automatically based on the
standard interrupt controls in the PCI Express Configuration Space registers. Software can write the
Interrupt Disable
bit, which is bit 10 of the
Command
register (at Configuration Space offset 0x4) to
disable legacy interrupts. Software can write the
MSI Enable
bit, which is bit 0 of the
MSI Control
Status
register in the MSI capability register (bit 16 at configuration space offset 0x50), to enable MSI
interrupts.
Software can only enable one type of interrupt at a time. However, to change the selection of MSI or
legacy interrupts during operation, software must ensure that no interrupt request is dropped. Therefore,
software must first enable the new selection and then disable the old selection. To set up legacy interrupts,
software must first clear the
Interrupt Disable
bit and then clear the
MSI enable
bit. To set up MSI
interrupts, software must first set the
MSI enable
bit and then set the
Interrupt Disable
bit.
8-2 Enabling MSI or Legacy Interrupts
UG-01145_avmm
2015.05.14
Altera Corporation Interrupts for Endpoints
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