Altera Arria 10 Avalon-MM User Manual
Page 62
Signal
Direction
Description
tx_deemph0
Output
Transmit de-emphasis selection. The Arria 10 Hard IP for PCI
Express sets the value for this signal based on the indication
received from the other end of the link during the Training
Sequences (TS). You do not need to change this value.
rxdata0[31:0]
(2)
Input
Receive data <n>. This bus receives data on lane <n>.
rxdatak[3:0]
(2)
Input
Receive data >n>. This bus receives data on lane <n>. Bit 0
corresponds to the lowest-order byte of
rxdata
, and so on. A
value of 0 indicates a data byte. A value of 1 indicates a control
byte. For Gen1 and Gen2 only.
rxblkst0
Input
For Gen3 operation, indicates the start of a block in the receive
direction.
txdetectrx0
Output
Transmit detect receive <n>. This signal tells the PHY layer to
start a receive detection operation or to begin loopback.
txelecidle
Output
Transmit electrical idle <n>. This signal forces the TX output to
electrical idle.
txcompl0
Output
Transmit compliance <n>. This signal forces the running
disparity to negative in Compliance Mode (negative COM
character).
rxpolarity0
Output
Receive polarity <n>. This signal instructs the PHY layer to
invert the polarity of the 8B/10B receiver decoding block.
powerdown0[1:0]
Output
Power down <n>. This signal requests the PHY to change its
power state to the specified state (P0, P0s, P1, or P2).
currentcoeff0[17:0]
Output
For Gen3, specifies the coefficients to be used by the transmitter.
The 18 bits specify the following coefficients:
• [5:0]: C
-1
• [11:6]: C
0
• [17:12]: C
+1
currentrxpreset0[2:0]
Output
For Gen3 designs, specifies the current preset.
tx_margin[2:0]
Output
Transmit V
OD
margin selection. The value for this signal is based
on the value from the
Link Control 2
Register
. Available for
simulation only.
UG-01145_avmm
2015.05.14
PIPE Interface Signals
5-15
64- or 128-Bit Avalon-MM Interface to the Application Layer
Altera Corporation