Altera Arria 10 Avalon-MM - Manual (Page 129)

Related Information
Avalon-MM RX Master Block on page 10-20
Avalon‑MM Bridge TLPs
The PCI Express to Avalon-MM bridge translates the PCI Express read, write, and completion Transac‐
tion Layer Packets (TLPs) into standard Avalon-MM read and write commands typically used by master
and slave interfaces. This PCI Express to Avalon-MM bridge also translates Avalon-MM read, write and
read data commands to PCI Express read, write and completion TLPs. The following topics describe the
Avalon-MM bridges translations.
Avalon-MM-to-PCI Express Write Requests
The Avalon-MM bridge accepts Avalon-MM burst write requests with a burst size of up to 512 Bytes at
the Avalon-MM TX slave interface. The Avalon-MM bridge converts the write requests to one or more
PCI Express write packets with 32– or 64-bit addresses based on the address translation configuration, the
request address, and the maximum payload size.
The Avalon-MM write requests can start on any address in the range defined in the PCI Express address
table parameters. The bridge splits incoming burst writes that cross a 4 KByte boundary into at least two
separate PCI Express packets. The bridge also considers the root complex requirement for maximum
payload on the PCI Express side by further segmenting the packets if needed.
The bridge requires Avalon-MM write requests with a burst count of greater than one to adhere to the
following byte enable rules:
• The Avalon-MM byte enables must be asserted in the first qword of the burst.
• All subsequent byte enables must be asserted until the deasserting byte enable.
• The Avalon-MM byte enables may deassert, but only in the last qword of the burst.
Note: To improve PCI Express throughput, Altera recommends using an Avalon-MM burst master
without any byte-enable restrictions.
Avalon-MM-to-PCI Express Upstream Read Requests
The PCI Express Avalon-MM bridge converts read requests from the system interconnect fabric to PCI
Express read requests with 32-bit or 64-bit addresses based on the address translation configuration, the
request address, and the maximum read size.
The Avalon-MM TX slave interface of a PCI Express Avalon-MM bridge can receive read requests with
burst sizes of up to 512 bytes sent to any address. However, the bridge limits read requests sent to the PCI
Express link to a maximum of 256 bytes. Additionally, the bridge must prevent each PCI Express read
request packet from crossing a 4 KByte address boundary. Therefore, the bridge may split an Avalon-MM
read request into multiple PCI Express read packets based on the address and the size of the read request.
Avalon-MM bridge supports up to eight outstanding reads from Avalon-MM interface. Once the bridge
has eight outstanding read requests, the
txs_waitrequest
signal is asserted to block additional read
requests. When a read request completes, the Avalon-MM bridge can accept another request.
For Avalon-MM read requests with a burst count greater than one, all byte enables must be asserted.
There are no restrictions on byte enables for Avalon-MM read requests with a burst count of one. An
invalid Avalon-MM request can adversely affect system functionality, resulting in a completion with the
abort status set. An example of an invalid request is one with an incorrect address.
UG-01145_avmm
2015.05.14
Avalon‑MM Bridge TLPs 10-11
IP Core Architecture Altera Corporation
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