Altera Arria 10 Avalon-MM - Manual (Page 201)

Debugging
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2015.05.14
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As you bring up your PCI Express system, you may face a number of issues related to FPGA configura‐
tion, link training, BIOS enumeration, data transfer, and so on. This chapter suggests some strategies to
resolve the common issues that occur during hardware bring-up.
Simulation Fails To Progress Beyond Polling.Active State
If your PIPE simulation cycles between the Detect.Quiet, Detect.Active, and Polling.Active LTSSM states,
the PIPE interface width may be incorrect. The width DUT top-level PIPE interface is 32 bits for Arria 10
devices.
Make the changes shown in the following table for the 32-bit PIPE interface.
Table 15-1: Changes for 32-Bit PIPE Interface
8-Bit PIPE Interface 32-Bit PIPE Interface
output wire [7:0] pcie_a10_hip_0_
hip_pipe_txdata0
output wire [31:0] pcie_a10_hip_0_hip_pipe_txdata0
input wire [7:0] pcie_a10_hip_0_
hip_pipe_rxdata0
input wire [31:0] pcie_a10_hip_0_hip_pipe_rxdata0
output wire pcie_a10_simulation_
inst_pcie_a10_hip_0_hip_pipe_
txdatak0
output wire [3:0] pcie_a10_simulation_inst_pcie_a10_
hip_0_hip_pipe_txdatak0
input wire pcie_a10_simulation_
inst_pcie_a10_hip_0_hip_pipe_
rxdatak0
input wire [3:0] pcie_a10_simulation_inst_pcie_a10_
hip_0_hip_pipe_rxdatak0
Hardware Bring-Up Issues
Typically, PCI Express hardware bring-up involves the following steps:
1. System reset
2. Link training
3. BIOS enumeration
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